Information processing apparatus and method and recording medium

ABSTRACT

A control machine which uses a data amount stored in a FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for the DMA transfer. The control machine for preparing for the DMA transfer issues the prepared command to a control machine for transferring DMA data, so that a process according to the command is started. At the time of the DMA transfer, the burden on the host CPU is reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 09/913,688filed on Nov. 14, 2001, which is a national phase entry under 35 U.S.C.§ 371 of International Application No. PCT/JP00/08892 filed Dec. 15,2000, published in Japanese, which claims priority from JP 11-358634filed Dec. 17, 1999.

BACKGROUND OF THE INVENTION

The invention relates to information processing apparatus and method anda recording medium and, more particularly, to information processingapparatus and method and a recording medium which are suitable forreducing a burden of a host CPU when a DMA transfer is performed.

In recent years, digital broadcast has been started in earnest andvarious digital broadcast receiving apparatuses have been put intopractical use. Among those apparatuses, there is an apparatus havingtherein a storage device such as a hard disk or the like for recordingthe received digital broadcast program. FIG. 1 shows an example of aconstruction of a conventional apparatus such that a hard disk drive 15serving as a storage device is built in a digital broadcast receivingapparatus for receiving digital broadcast.

The digital broadcast receiving apparatus receives a transport stream asa digital broadcast program from a broadcast station (not shown) and canperform a display or the like of an image and sound as a transportstream. Further, after the transport stream was recorded, the apparatuscan also reproduce the recorded transport stream.

That is, a digital broadcast wave is received by an antenna 11 and thereception signal is outputted to a tuner 12. The tuner 12 performs ademodulation or the like of the reception signal from the antenna 11,obtains the transport stream, and supplies it to a descrambler 13. Undera control of a CPU 1, the descrambler 13 descrambles the scrambleperformed to the transport stream from the tuner 12 by using a decodingkey that is supplied from the CPU 1 and outputs the descrambledtransport stream to a hard disk control unit 14.

The transport stream (hereinafter, properly referred to as a receptiontransport stream) which is outputted from the descrambler 13 is suppliedto a PID (Packet Identification) parser 21 and a switch 31 in the harddisk control unit 14. Besides the reception transport stream, atransport stream which is reproduced from the hard disk drive 15 is alsosupplied to the switch 31 through a transmitter 26.

In case of reproducing the reception transport stream, the switch 31selects the reception transport stream from the two transport streams(reception transport stream and transport stream which is supplied fromthe transmitter 26) which are inputted to the switch 31 and outputs itas an output transport stream to an MVLink-IC (MPEG (Moving PictureExperts Group) Link Integrated Circuit)) 16.

The MVLink-IC 16 performs a process or the like of a link layer in alayer structure of an IEEE (Institute of Electrical and ElectronicsEngineers) 1394 serial bus to the output transport stream and outputsthe resultant transport stream to a PHY-IC 17, or the MVLink-IC 16 sendsthe output transport stream to a DEMUX (demultiplexer) 18.

The PHY-IC 17 executes the process of the link layer in the layerstructure of the IEEE1394 serial bus. When the output transport streamis received from the MVLink-IC 16, the PHY-IC 17 isochronously transfersthe output transport stream to an IEEE1394 apparatus (not shown) throughthe IEEE1394 serial bus.

The DEMUX 18 has a microcomputer, a memory, and the like (not shown).The DEMUX 18 separates a TS packet in which data (PAT (ProgramAssociation Table) or PMT (Program Map Table)), the decoding key fordescrambling the scramble of the transport stream, and control datawhich is used for the other control of a section have been arranged froma transport packet (hereinafter, properly referred to as a TS packet)constructing the output transport stream from the MVLink-IC 16, further,analyzes the contents of the TS packet, and outputs necessary controldata to the CPU 1.

As mentioned above, the CPU 1 outputs the decoding key in the data ofthe section supplied from the DEMUX 18 to the descrambler 13 andcontrols the descrambler 13 on the basis of data of another sectionwhich is likewise supplied from the DEMUX 18.

In addition to the separation of the TS packet in which the control data(data of the section) has been arranged from the output transportstream, the DEMUX 18 separates a packet in which video data and audiodata (hereinafter, both of them are properly collectively referred to asAV data) of a program selected by the user by operating a remotecommander or the like (not shown) have been arranged and outputs thepacket to an AV decoder 19. The AV decoder 19 MPEG2-decodes the TSpacket from the DEMUX 18 and outputs the resultant AV data to a monitor(not shown). Thus, an image and an audio sound as a digital satellitebroadcast program are outputted (displayed) by the monitor.

In case of recording the reception transport stream, the switch 31selects likewise the reception transport stream from the two transportstreams (the reception transport stream and the transport streamsupplied from the transmitter 26) which are inputted to the switch 31and outputs it as an output transport stream to the DEMUX 18 via theMVLink-IC 16.

As mentioned above, the DEMUX 18 separates the TS packet in which thecontrol data has been arranged from the output transport stream,separates the necessary control data arranged in the TS packet, andoutputs it to the CPU 1. The CPU 1 controls the descrambler 13 on thebasis of the control data. Thus, the descrambling of the transportstream including the TS packet serving as a recording target at presentis executed in the descrambler 13.

As mentioned above, the reception transport stream is also supplied tothe PID parser 21. The PID parser 21 refers to a PID of the TS packetsconstructing the reception transport stream supplied to the parser 21and supplies only the TS packets regarding the program as a recordingtarget to a receiver 22 (the remaining TS packets are abandoned). Thereceiver 22 adds a time stamp based on a clock which is generated from acycle timer 27 to the TS packets from the PID parser 21 and supplies theresultant TS packets to an input FIFO (First In First Out) 23. That is,the cycle timer 27 outputs the clock of a predetermined frequency to thereceiver 22 and transmitter 26. The receiver 22 adds the time stampsynchronized with the clock which is outputted from the cycle timer 27to the TS packets from the PID parser 21 and outputs the resultant TSpacket to the input FIFO 23. The input FIFO 23 sequentially stores theTS packets from the receiver 22 and outputs the stored TS packets to ahard disk I/F (interface) 24 in the storing order in accordance with acontrol of a controller 28.

The controller 28 has a microcomputer therein, monitors a status ofstorage in the input FIFO 23 or an output FIFO 25, and controls thereading and writing operations of data in each FIFO. The controller 28also controls the hard disk I/F 24.

When the TS packets are received from the input FIFO 23, the hard diskI/F 24 outputs the TS packets to the hard disk drive 15. In the harddisk drive 15, the TS packets from the hard disk I/F 24 are received bya hard disk controller 41 and recorded onto a hard disk 42.

Subsequently, in case of reproducing the TS packets recorded on the harddisk 42 as mentioned above, the transport stream (hereinafter, properlyreferred to as a reproduction transport stream) as a sequence of the TSpackets recorded on the hard disk 42 is read out and outputted to thehard disk control unit 14 by the hard disk controller 41.

In the hard disk control unit 14, the reproduction transport stream isreceived and supplied to the output FIFO 25 by the hard disk I/F 24. Theoutput FIFO 25 sequentially stores the TS packets constructing thereproduction transport stream from the hard disk I/F 24 and outputs thestored TS packets to the transmitter 26 in the storing order inaccordance with the control of the controller 28.

The transmitter 26 outputs the reproduction transport stream as asequence of the TS packets from the output FIFO 25 to the switch 31synchronously with the clocks supplied from the cycle timer 27. That is,in the case where the transport stream as a sequence of the TS packetswhich are outputted by the PID parser 21 is recorded to the hard diskdrive 15, there is a case where time intervals of the TS packetsconstructing the transport stream are lost. Therefore, the transmitter26 refers to the time stamps added to the TS packets by the receiver 22and outputs the TS packets to the switch 31 at timing such that the timeintervals of the TS packets are returned to the original state.

In case of reproducing the TS packets recorded on the hard disk 42, theswitch 31 selects the reproduction transport stream which is outputtedfrom the transmitter 26 and outputs it as an output transport stream tothe MVLink-IC 16. In a manner similar to the case of processing thereception transport stream, hereinafter, the reproduction transportstream as an output transport stream is isochronously transferred on theIEEE1394 serial bus through the PHY-IC 17 or outputted to the monitorthrough the DEMUX 18 and decoder 19.

The CPU 1 is connected to a bus 3 and reads out and executes a programstored in a system memory 2 likewise connected to the bus 3, therebyexecuting the control of the descrambler 13 and various other processes.The program for allowing the CPU 1 to execute the various processes hasbeen stored in the system memory 2.

A host I/F 29 constructing the hard disk control unit 14 functions as aninterface for communicating with the CPU 1 through the bus 3. Aninput/output buffer 30 provided between the host I/F 29 and theforegoing hard disk I/F 24 temporarily stores the data which istransmitted and received therebetween.

Consequently, the CPU 1 can access to the hard disk drive 15 through thebus 3, host I/F 29, I/O buffer 30, and hard disk I/F 24. Therefore, theCPU 1 can record the data as a file onto the hard disk drive 15 and readout the data as a file recorded on the hard disk drive 15.

The minimum unit of the recording of the data on the hard disk drive 15is called a sector. One sector consists of, for example, 512 bytes.Further, specifications of an interface and a using method of the harddisk drive 15 have been unified in a manner such that when it accessesto the data, an accessing location on the hard disk drive 15 isdesignated by a sector address as a minimum recording unit. The harddisk drive 15 has a construction such that when it is accessed to thedata, unless the accessing location is designated by the sector address,it is not accepted as a command.

The address of the minimum unit is expressed by a logical serial numbercalled LBA (Logical Block Address). As commands to access to the harddisk drive 15, there are a DMA (Direct Memory Access) in which the datatransfer is controlled by a DMA controller and a PIO (Programmed I/O) inwhich the data transfer is controlled by the CPU. In both cases, it isnecessary to use the LBA for address designation.

In the foregoing conventional digital video broadcast receivingapparatus, in the case where an AV (Audio Visual) stream such as atransport stream is recorded onto the built-in hard disk or read out andreproduced from the hard disk by the DMA, it is necessary that a hostCPU (Central Processing Unit) executes the issuance of a command to thehard disk, the setting of the LBA at every block transfer, the settingof transfer start timing, and the like. There is a problem such thatthose processes become a burden on the host CPU and high performancecannot be effected.

Therefore, there is a problem such that there is a possibility that, forexample, while the recording process of the AV stream is being executed,the stream cannot be continuously recorded.

SUMMARY OF THE INVENTION

The invention is made in consideration of such a situation and it is anobject of the invention that by providing a register for DMA transferand a function which can automatically set an LBA, the issuance of acommand, the setting of the LBA, and the setting of transfer starttiming which have conventionally been processed by a host CPU areexecuted on a DMA side and the burden on the host CPU as mentioned aboveis reduced.

According to the invention, to solve the above problems, there isprovided an information processing apparatus including a receiver forreceiving a stream of packets of a predetermined format; an extractingunit operable to extract packets which are recorded to a recordingapparatus from the stream of packets received by the receiver; a memoryfor storing the extracted packets; a command buffer for forming acommand for instructing a DMA transfer; and a transfer unit operable toDMA-transfer the packets to the recording apparatus by using the packetsas a block of a predetermined data amount in accordance with the commandformed in the command buffer.

According to the invention, there is provided an information processingapparatus including a receiver for receiving a stream of packets of apredetermined format; an extracting unit operable to extract packetswhich are recorded to a recording apparatus from the stream of packetsreceived by the receiver; a memory for storing the extracted packets; acommand buffer for setting address information for DMA transfer; and anadder for adding the address information every predetermined data amount(block) of packets read out from the memory.

According to the invention, there is provided a digital broadcastreceiving apparatus including a hard disk drive; a receiver forreceiving a stream of packets of a predetermined format; an extractingunit operable to extract packets which are recorded into the hard diskdrive from the stream of packets received by the receiver; a memory forstoring the extracted packets; a command buffer for forming a commandfor instructing a DMA transfer; and a transfer unit operable toDMA-transfer the packets to the hard disk drive by using the packets asa block of a predetermined data amount in accordance with the commandformed in the command buffer.

According to the invention, there is provided a digital broadcastreceiving apparatus including a hard disk drive; a receiver forreceiving a stream of packets of a predetermined format; an extractingunit operable to extract packets which are recorded into the hard diskdrive from the stream of packets received by the receiver; a memory forstoring the extracted packets; a command buffer for setting addressinformation for DMA transfer; and an adder for adding the addressinformation every predetermined data amount (block) of packets read outfrom the memory.

According to the invention, there is provided an information processingmethod including receiving a stream of packets of a predeterminedformat; extracting packets which are recorded to a recording apparatusfrom the received stream of packets; storing the extracted packets in amemory; forming a command for instructing a DMA transfer using a commandbuffer; and DMA-transferring the packets to the recording apparatus byusing the packets as a block of a predetermined data amount inaccordance with the command formed in the forming step.

According to the invention, there is provided an information processingmethod including receiving a stream of packets of a predeterminedformat; extracting packets which are recorded to a recording apparatusfrom the received stream of packets; storing the extracted packets in amemory; setting address information for DMA transfer using a commandbuffer; and adding the address information every predetermined dataamount (block) of the packets read out from the memory.

According to the invention, there is provided a recording mediumrecorded with a computer-readable program for causing a computer toperform an information processing method, the method including receivinga stream of packets of a predetermined format; extracting packets whichare recorded to a recording apparatus from the received stream ofpackets; storing the extracted packets in a memory; forming a commandfor instructing a DMA transfer using a command buffer; andDMA-transferring the packets to the recording apparatus by using thepackets as a block of a predetermined data amount in accordance with thecommand formed in the forming step.

According to the invention, there is provided a recording mediumrecorded with a computer-readable program for causing a computer toperform an information processing method, the method including receivinga stream of packets of a predetermined format; extracting packets whichare recorded to a recording apparatus from the received stream ofpackets; storing the extracted packets in a memory; setting addressinformation for DMA transfer using a command buffer; and adding theaddress information every predetermined data amount (block) of packetsread out from the memory.

As mentioned above, according to the invention, the stream of packets ofthe predetermined format is received, the packets which were extractedfrom the stream of packets received and recorded to the recordingapparatus are stored, and the packets are DMA transferred to therecording apparatus in accordance with a command which was formed in thecommand buffer and which instructs the DMA transfer by using the packetsas a block of the predetermined data amount. Thus, the burden on a hostCPU is reduced.

According to the invention, the stream of packets of the predeterminedformat is received, the packets which were extracted from the stream ofpackets received and recorded to the recording apparatus are stored inthe memory, and the address information for DMA transfer set by thecommand buffer is added every predetermined data amount (block) of thepackets read out from the memory. Thus, the burden on the host CPU isreduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of a construction of adigital satellite broadcast receiving apparatus having a hard disk drivetherein;

FIG. 2 is a block diagram showing an example of a construction of anembodiment of a digital satellite broadcast receiving apparatus to whichthe invention is applied;

FIG. 3 is a block diagram showing an example of a construction of a harddisk control unit in FIG. 2;

FIG. 4 is a block diagram showing a construction of a DMA controller inFIG. 3;

FIG. 5 is a block diagram showing a construction of a command cell inFIG. 4;

FIG. 6 is a block diagram showing a construction of an LBA determiningunit in FIG. 5;

FIG. 7 is a functional block diagram of the DMA controller;

FIG. 8 is a flowchart for explaining the writing operation of the DMAcontroller;

FIG. 9 is a flowchart for explaining the reading operation of the DMAcontroller;

FIG. 10 is a diagram for explaining reading timing;

FIG. 11 is a flowchart for explaining the operation which is executed atthe time of the DMA transfer of the DMA controller;

FIG. 12 is a diagram for explaining registers;

FIG. 13 is a diagram for explaining the registers; and

FIG. 14 is a diagram for explaining a medium.

DETAILED DESCRIPTION

FIG. 2 shows a construction of an embodiment of a digital satellitebroadcast receiving apparatus to which the invention is applied. In thediagram, portions corresponding to those in FIG. 1 mentioned above aredesignated by the same reference numerals and their descriptions areproperly omitted hereinbelow. That is, the digital satellite broadcastreceiving apparatus of FIG. 2 is constructed in a manner similar to thedigital satellite broadcast receiving apparatus of FIG. 1 except for apoint that a hard disk control unit 50 is provided in place of the harddisk control unit 14 shown in FIG. 1.

FIG. 3 shows an example of a construction of the hard disk control unit50 in FIG. 2. In the diagram, portions corresponding to those in thehard disk control unit 14 in FIG. 1 are designated by the same referencenumerals and their descriptions are properly omitted hereinbelow.

The reception transport stream from the descrambler 13 is supplied tothe switch 31 and an input PID parser 51. From the TS packetsconstructing the reception transport stream from the descrambler 13, theinput PID parser 51 extracts: a TS packet to be subjected only to therecording (hereinafter, such a TS packet is properly referred to as arecording packet); a TS packet which is recorded and used for control(hereinafter, such a TS packet is properly referred to as arecording/control packet); a TS packet which is used only for control(hereinafter, such a TS packet is properly referred to as a controlpacket); and a TS packet to be abandoned (hereinafter, such a TS packetis properly referred to as an abandonment packet). The input PID parser51 outputs the recording packet and the recording/control packet to timestamp adding unit 56 and outputs the control packet to an MUX 53.Further, the input PID parser 51 abandons the abandonment packet.

An output PID parser 52 receives a reproduction transport stream whichis outputted from a time stamp detecting unit 54 and reproduced from thehard disk drive 15 and extracts a TS packet to be reproduced(hereinafter, such a TS packet is properly referred to as a reproducingpacket) and a TS packet to be abandoned (abandonment packet) from the TSpackets constructing the reproduction transport steam. Further, theoutput PID parser 52 outputs the reproducing TS packet to the MUX 53 andabandons the abandonment packet.

By communicating with the MUX 53, the output PID parser 52 detects thereproducing TS packet whose PID is equal to that of the TS packet thatis outputted to the MUX 53 by the input PID parser 51 and changes thePID of the reproducing TS packet to a different PID. The MUX 53multiplexes the TS packet which is outputted from the input PID parser51 and the TS packet which is outputted from the output PID parser 52and outputs the multiplexed packet to the switch 31.

The time stamp adding unit 56 and an input timer 57 executes processessimilar to those of the cycle timer 27 and receiver 22 in FIG. 1. Thatis, the time stamp adding unit 56 adds time stamps based on clocks whichare outputted from the input timer 57 to the inputted TS packets. The TSpackets to which the time stamps were added by the time stamp addingunit 56 are inputted to an arbiter 58. The TS packets inputted to thearbiter 58 are stored into an input FIFO 61 of an SDRAM 60 under thecontrol of an SDRAM controller 59. In response to an instruction from anFIFO controller 63, the SDRAM controller 59 controls the writing andreading operations of the packets into the input FIFO 61 and from anoutput FIFO 62 of the SDRAM 60.

The TS packets stored in the input FIFO 61 are read out under thecontrol of an SDRAM controller 59 and outputted to an index adding unit64 through the arbiter 58. The index adding unit 64 adds the LBA showingan address on the hard disk and information that is effective foranother control as indices and outputs them to a selector 67. Datainputted through a bus interface 29, a command from a DMA controller 68,and the like are also inputted to the selector 67. The selector 67selects the inputted TS packets, data, command, etc. and outputs theselected one to a predetermined apparatus. For example, the TS packetswhich were outputted from the index adding unit 64 and inputted to theselector 67 are outputted to the hard disk I/F 24 and, further,outputted to the hard disk drive 15 and recorded.

In case of reproducing the TS packets recorded in the hard disk drive 15as mentioned above, in the hard disk controller 41, the reproductiontransport stream as a sequence of the TS packets recorded on the harddisk 42 is read out and outputted to the hard disk control unit 50. Thereproduction transport stream inputted to the hard disk control unit 50through the hard disk I/F 24 is outputted to an index detecting unit 66through the selector 67.

The index detecting unit 66 detects the index added by the index addingunit 64 from the inputted reproduction transport stream. The detectedindex is stored into a register in the DMA controller 68. On the basisof the stored index, the DMA controller 68 can also control the DMAcontroller 68.

The index is detected by the index detecting unit 66 and thereproduction transport stream from which the index was removed is oncestored into the output FIFO 62 of the SDRAM 60 through the arbiter 58and SDRAM controller 59. The reproduction transport stream stored in theoutput FIFO 62 is read out to the arbiter 58 under the control of theSDRAM controller 59 and, further, outputted to the time stamp detectingunit 54. The time stamp is detected from the reproduction transportstream inputted to the time stamp detecting unit 54 and the reproductiontransport stream is outputted to the output PID parser 52 in accordancewith the time stamp. Further, the processes as mentioned above areexecuted by the MUX 53 and switch 31, so that the resultant data isoutputted to the MVLink-IC 16.

With respect to the data which is transmitted and received to/from thehard disk 15, a CRC 69 checks the data by using a CRC (Cyclic RedundancyCheck).

FIG. 4 is a diagram showing an internal construction of the DMAcontroller 68. An internal bus 81 in the DMA controller 68 is connectedto the bus I/F 29. A command cell 82, a command arbiter 83 forcontrolling the command cell 82, a PIO (Programmed I/O) state machine 84for controlling the operation at the time of transmitting and receivingthe data through the CPU 1 as a host CPU, and a host data DMA buffer 85for buffering the data at the time of the DMA transfer are connected tothe internal bus 81.

A DMA state machine 86 prepares for a register and a command forexecuting the DMA transfer in an interlocking relational manner with thecommand cell 82. An IDE (Intelligent Drive Electronics) state machine 87controls the hard disk drive 15 which is connected by an IDE drive. ThePIO state machine 84, DMA state machine 86, and IDE state machine 87 aremutually connected by control lines and each state machine can perform acontrol according to a situation.

Signals outputted from the PIO state machine 84 and DMA state machine 86are supplied to a selector 88 and one of those signals is supplied to anAND circuit 89. A signal from the IDE state machine 87 is also suppliedto the AND circuit 89. The AND is obtained from the supplied signals andits result is outputted to an internal bus 91. The control line from theIDE state machine 87 is also connected to the internal bus 91 and acontrol signal of the IDE is also supplied.

Further, a signal from a selector 90 is also supplied to the internalbus 91. The selector 90 selects one of the data from the PIO statemachine 84, the data from the DMA state machine 86, and the data fromthe FIFO controller 63 and outputs it to the internal bus 91.

FIG. 5 is a diagram showing an internal construction of the command cell82. A host command buffer 102 and a host data command buffer 103 areconnected to an internal bus 101. Although the details will be explainedhereinlater, data which is stored in a next command buffer 105 at thepost stage is formed from data which is outputted from the host commandbuffer 102 and an LBA determining unit 104. As for the data stored inthe next command buffer 105, when new data is inputted, the stored datais outputted to a current command buffer 106 and stored. Similarly, whennew data is inputted to the current command buffer 106, the stored datais outputted to a previous command buffer 107 and stored.

The command cell 82 has the host command buffer 102 for initializing theDMA transfer by the PIO access and has a role like an FIFO for shiftingthe contents in the command buffer each time the current DMA transfer isfinished. As for each command buffer, although it is necessary toprepare a buffer for writing and a buffer for reading, only one bufferis shown in FIG. 5. By the command buffers with the FIFO-likeconstruction, the next, current, and previous LBAs can be added as anindex every cluster.

The current LBA indicates a head LBA in which the block processed atthis time point is recorded. The previous LBA indicates a head LBA ofthe block locating just before a block N. The next LBA indicates a headLBA of the block locating just after the block N.

The data stored in the next command buffer 105, current command buffer106, and previous command buffer 107 is supplied to a selector 108,respectively. The data from the host data command buffer 103 is alsosupplied to the selector 108. The selector 108 selects one of thesupplied data and outputs it to the DMA state machine 86. The selecteddata comprises an LBA which is necessary for activating the DMA transferof the hard disk, a sector size, and the like. The control of the harddisk can be performed by supplying those information to the DMA statemachine 86 and IDE state machine 87.

FIG. 6 is a diagram showing an internal construction of the LBAdetermining unit 104. The LBA determining unit 104 comprises a count-upunit 121, a register for LBA comparison 122, and a comparing unit 123.

When the DMA controller 68 having the construction as mentioned above isshown by a functional block, it is as shown in FIG. 7. A control machine131 to start the DMA transfer according to a capacity of the FIFO mainlycomprises the FIFO controller 63 and command arbiter 83. A controlmachine 132 to prepare for the DMA transfer mainly comprises the commandcell 82 and DMA state machine 86. A control machine 133 to perform thePIO access is the PIO state machine 84. A control machine 134 to performthe DMA transfer mainly comprises the IDE state machine 87. A commandbuffer 135 mainly comprises the command cell 82. An LBA determiningcircuit 136 is the LBA determining unit 104.

Subsequently, the operation of the control machine 131 to start the DMAtransfer according to the capacity of the FIFO will be described withreference to a flowchart of FIG. 8. It is assumed that the DMA transferis executed on a 128-kbyte unit basis and the unit of 128 kbytes isdefined as one cluster. Naturally, one cluster can be also defined bybytes of 128 kbytes or less.

In case of writing the received transport stream into the hard diskdrive 15, in step S1, the command arbiter 83 discriminates whether thetransport stream has been stored in the capacity which is equal to orlarger than a predetermined value of the input FIFO 61 or not throughthe FIFO controller 63. The predetermined value is a capacity of, forexample, 80% of that of the input FIFO 61. In step S1, whether the inputFIFO is in a state where the data of the transport stream has alreadybeen written into the capacity of 80% or more or not is discriminated.

If it is determined in step S1 that the transport stream has been storedin the capacity that is equal to or larger than the predeterminedcapacity of the input FIFO 61, step S2 follows. In step S2, aninstruction to start the DMA transfer is issued to the control machine132 for preparing for the DMA transfer. A start LBA is supplied to theLBA determining circuit 136. Thus, the control machine 132 for preparingfor the DMA transfer discriminates about which one of the three requestsfor the reading of the stream, the writing thereof, and the host dataaccess the control machine 132 to prepare for the DMA transfer permitsin step S3.

If the writing of the stream is permitted in step S4, step S5 followsand whether an end status has been issued or not is discriminated. Theend status is issued by the control machine 132 to prepare for the DMAtransfer. The processin step S5 is repeated until it is decided that theend status was issued. If it is determined that the end status wasissued, step S6 follows and an instruction to update the LBA is issuedto the LBA determining unit 104.

The updating of the LBA is performed by the LBA determining unit 104(LBA determining circuit 136). When the start LBA is inputted, thecount-up unit 121 starts the count-up operation. Each time the transferof the data of one cluster is finished, the count-up unit 121 counts upand sets the LBAs of one cluster. The register 122 for LBA comparisonsets flags for the LBA to be compared and the next LBA. When the flagsare valid, by replacing the comparison LBA with the next LBA, theregister 122 can change the value which is automatically set. Byproviding such a function and setting the maximum LBA of the memory areaof the transport stream into the register, the LBA can be automaticallyreturned to the start LBA of the memory capacity.

The LBA which is updated as mentioned above is supplied not only to theDMA state machine 86 but also to the index adding unit 64 and added whenthe transport stream as a processing target is stored into the hard diskdrive 15. The processes of the flowchart shown in FIG. 8 arerepetitively executed when the received transport stream is stored intothe hard disk drive 15.

FIG. 9 is a flowchart for explaining processes at the time of readingout the transport stream stored in the hard disk drive 15.Fundamentally, the processes of FIG. 9 are similar to those upon writingdescribed with reference to the flowchart of FIG. 8 except for a pointsuch that the write permission of the stream in step S4 in FIG. 8 ischanged to step S4′ as a process for read permission of the stream.Therefore, their descriptions are omitted. In the process in step S1′,however, whether the data amount of the transport stream stored in theoutput FIFO 62 is equal to or less than, for example, 20% as apredetermined value or not is discriminated. If it is determined that itis equal to or less than the predetermined value, the processing routineadvances to the processes in step S2 and subsequent steps.

The data of the transport stream which is read out from the hard diskdrive 15 will now be described with reference to FIG. 10. It is alsopossible to use a method whereby the LBA to be read out next forpredetermined data is read out from the value of the next LBA in theindex information of the block which has already been read out and set.The LBA can be also set by the automatic updating of the LBA. In case ofusing such a method, by notifying the CPU 1 of the interruption at apoint of completion of the reading of the index information, the nextLBA can be dynamically changed at timing shown in FIG. 10.

In FIG. 10, reference character “a” denotes timing at which an LBA linklist in the index read out from the hard disk drive 15 is actuallyloaded into a reproduction next LBA register (not shown). By notifyingthe interruption at this timing, the host reads the next LBA or currentLBA at timing “b”. If the user wants to dynamically change the LBA of acluster to be read out next and perform a skip reproduction, the writingis executed at timing “c”. Reference character “d” denotes timing atwhich the DMA controller 68 automatically issues a command to the harddisk drive 15 with reference to the data which is outputted from theoutput FIFO 62 and indicates that almost the half of the capacity hasbeen recorded.

The CPU 1 can also set the LBA into the DMA command buffer for writingor reading and control the DMA. In such a case, after the value is setinto each command set register, by setting “1” into each command Execbit in the control register, the command is executed. At this time, theDMA transfer to the hard disk drive 15 can be also automaticallyperformed by a trigger of an FIFO flag by the setting irrespective ofthe control of the CPU 1. In such a case, when each Valid bit in thecontrol register is equal to “1”, the DMA transfer is alternatelyexecuted in accordance with the contents in the command buffer.

If the operation is finished before all of the data of one cluster isread out after the data was inputted to the output FIFO 62 due to somereason upon reproduction, by returning the current address pointer ofthe output FIFO 62, the data can be consequently abandoned. Thus, evenif an error occurs, the operation can be recovered to a normalreproducing mode of the AV stream without passing through the CPU 1.

The operations of the control machine 132 for preparing for the DMAtransfer and the command buffer 135 for supplying the command to thecontrol machine 132 for preparing for the DMA transfer will now bedescribed with reference to a flowchart of FIG. 11. In step S21, thestatus is read out in response to the start instruction from the controlmachine 131 for starting the DMA transfer according to the capacity ofthe FIFO. Whether the access is possible or not is discriminated in stepS22 on the basis of the read-out status. The process in step S22 isrepeated until it is determined that the access is possible. If it isdetermined that the access is possible, step S23 follows.

The data is written into device/head registers in step S23. Theregisters will now be described. FIG. 12A is a diagram showing thespecification of registers of the IDE and showing a list of theregisters. Among the control block registers in FIG. 12A, a devicecontroller is a register as shown in FIG. 12B.

Among the command block registers in FIG. 12A, data is a register asshown in FIG. 12C and a sector number is a register as shown in FIG.12D. Further, among the command block registers in FIG. 12A,cylinder•low and cylinder•high are registers as shown in FIG. 13A,device/head are registers as shown in FIG. 13B, sector•counter is aregister as shown in FIG. 13C, and substitute status and status areregisters as shown in FIG. 13D, respectively.

The registers as mentioned above exist. Among them, the data is writteninto the device/head registers in step S23. The status is read out instep S24. Whether a result of the read-out status indicates a busystatus or not is discriminated in step S25. The process in step S25 isrepeated until it is determined that the status is not the busy status.If it is decided that the status is not the busy status, step S26follows.

The writing into the cylinder•low•register is performed in step S26. Thewriting into the cylinder•high register is performed in step S27. Thewriting into the sector•number•register is performed in step S28. Thewriting into the sector•count•register is performed in step S29. In theregisters to which the writing has sequentially been performed asmentioned above, the data is written as a command of DMA write or DMAread in step S30.

The control machine 132 to prepare for the DMA transfer issues the DMAwrite or DMA read command to the control machine 134 for performing theDMA transfer in step S31 and the control machine 134 for performing theDMA transfer starts the DMA transfer in accordance with the receivedcommand. In step S32, the control machine 132 to prepare for the DMAtransfer discriminates whether the status is the end status or not. Ifit is determined that the status is the end status, step S33 follows.

In step S33, the control machine 132 to prepare for the DMA transferreceives the end status and outputs data indicative of the end of theDMA transfer to the control machine 131 for starting the DMA transferaccording to the capacity of the FIFO. The processes of the flowchartshown in FIG. 11 are repetitively executed each time the DMA transfer isstarted.

As mentioned above, by providing the command buffer for DMA transfer andproviding the function for updating the LBA, the burden on the host CPUcan be reduced. It is possible to perform the recording and reproductionwithout dropping out the AV stream.

Although the series of processes mentioned above can be executed byhardware, it can be also executed by software. In case of executing theseries of processes by software, the program constructing the softwareis installed into a computer built in dedicated hardware or, forexample, a general personal computer which can execute various functionsby installing various programs therein, or the like from a recordingmedium.

As shown in FIG. 14, the recording medium is constructed by providing adrive 140 for the digital satellite broadcast receiving apparatus and byusing a package media which is distributed to provide the program to theuser separately from the digital satellite broadcast receivingapparatus, wherein the package media comprises: a magnetic disk 151(including a floppy disk) in which the program has been recorded; anoptical disk 152 (including a CD-ROM (Compact Disk—Read Only Memory), aDVD (Digital Versatile Disk)); a magnetooptic disk 153 (including an MD(Mini-Disc)) ; a semiconductor memory 154; or the like. Moreover, therecording medium can be also constructed by an ROM, the hard disk 15, orthe like which is provided to the user in a state where it haspreviously been built in the computer and in which the program has beenstored.

In the specification, the step of describing the program which isprovided by the medium includes not only the processes which aretime-sequentially executed in accordance with the disclosed order butalso the processes which are executed in parallel or individuallywithout being time-sequentially processed.

According to the digital broadcast receiving apparatus of the invention,when the received AV stream is DMA transferred and recorded andreproduced, the command buffer for DMA transfer is provided, the commandfor transfer is formed, the LBA is automatically set, and the issuanceof the command, the setting of the LBA, and the setting of the transferstart timing which have conventionally been processed by the host CPUare executed on the DMA side. Thus, the burden on the host CPU can bereduced.

1. An information processing apparatus, comprising: a receiver forreceiving a stream of packets of a predetermined format; all extractingunit operable to extract packets which are recorded to a recordingapparatus from the stream of packets received by the receiver; a memoryfor storing the extracted packets; a command buffer for setting addressinformation for DMA transfer; and an adder for adding the addressinformation every predetermined data amount (block) of packets readoutfrom the memory.
 2. An information processing apparatus according toclaim 1, wherein the address information includes at least one of anaddress in the recording apparatus in which a just-previous block hasbeen recorded, an address in the recording apparatus in which a currentblock is recorded, and an address in the recording apparatus in which ajust-subsequent block is recorded.
 3. An information processingapparatus according to claim 1, further comprising an updating unitoperable to update the address information for DMA transfer.
 4. Aninformation processing apparatus according to claim 3, wherein theupdating unit has an internal counter for automatically setting theaddress information.
 5. An information processing apparatus according toclaim 4, wherein each time the DMA transfer of one block is finished,the internal counter is counted up and address information of one blockis set as the address information.
 6. An information processingapparatus according to claim 3, wherein the updating unit updates theaddress information for DMA transfer when the data amount of the packetsstored by the memory reaches a predetermined capacity.
 7. An informationprocessing apparatus according to claim 1, wherein the memory includesan input FIFO and an output FIFO.
 8. An information processing apparatusaccording to claim 7, further comprising an updating unit operable toupdate the address information for DMA transfer.
 9. An informationprocessing apparatus according to claim 8, wherein the updating unitupdates the address information for DMA transfer when the data amount ofthe packets stored in the input FIFO is equal to or larger than apredetermined capacity.
 10. An information processing apparatusaccording to claim 8, wherein the updating unit updates the addressinformation for DMA transfer when the data amount of the packets storedin the output FIFO is equal to or smaller than a predetermined capacity.11. An information processing apparatus according to claim 1, whereinthe recording apparatus is a hard disk drive built in the informationprocessing apparatus.
 12. A digital broadcast receiving apparatus,comprising: a hard disk drive; a receiver for receiving a stream ofpackets of a predetermined format; an extracting unit operable toextract packets which are recorded into the hard disk drive from thestream of packets received by the receiver; a memory for storing theextracted packets; a command buffer for setting address information forDMA transfer; and an adder for adding the address information everypredetermined data amount (block) of packets read out from the memory.13. A digital broadcast receiving apparatus according to claim 12,wherein the address information includes at least one of an address inthe hard disk drive in which a just-previous block has been recorded, anaddress in the hard disk drive in which a current block is recorded, andan address in the hard disk drive in which a just-subsequent block isrecorded.
 14. A digital broadcast receiving apparatus according to claim12, further comprising an updating unit operable to update the addressinformation for DMA transfer.
 15. A digital broadcast receivingapparatus according to claim 14, wherein the updating unit has aninternal counter for automatically setting the address information. 16.A digital broadcast receiving apparatus according to claim 15, whereineach time the DMA transfer of one block is finished, the internalcounter is counted up and address information of one block is set as theaddress information.
 17. A digital broadcast receiving apparatusaccording to claim 14, wherein the updating unit updates the addressinformation for DMA transfer when the data amount of the packets storedby the memory reaches a predetermined capacity.
 18. A digital broadcastreceiving apparatus according to claim 12, wherein the memory includesan input FIFO and an output FIFO.
 19. A digital broadcast receivingapparatus according to claim 18, further comprising an updating unitoperable to update the address information for DMA transfer.
 20. Adigital broadcast receiving apparatus according to claim 19, wherein theupdating unit updates the address information for DMA transfer when thedata amount of the packets stored in the input FIFO is equal to orlarger than a predetermined capacity.
 21. A digital broadcast receivingapparatus according to claim 19, wherein the updating unit updates theaddress information for DMA transfer when the data amount of the packetsstored in the output FIFO is equal to or smaller than a predeterminedcapacity.
 22. An information processing method, comprising: receiving astream of packets of a predetermined format; extracting packets whichare recorded to a recording apparatus from the received stream ofpackets; storing the extracted packets in a memory; setting addressinformation for DMA transfer using a command buffer; and adding theaddress information every predetermined data amount (block) of packetsread out from the memory.
 23. A recording medium recorded with acomputer-readable program for causing a computer to perform aninformation processing method, the method comprising: receiving a streamof packets of a predetermined format; extracting packets which arerecorded to a recording apparatus from the received stream of packets;storing the extracted packets in a memory; setting address informationfor DMA transfer using a command buffer; and adding the addressinformation every predetermined data amount (block) of packets read outfrom the memory.